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data sheet mos integr a ted circuit m pd61p24 description the m pd61p24 is a 4-bit single-chip microcontroller for infrared remote controllers for tvs, vcrs, stereos, cassette decks, air conditioners, etc. as the m pd61p24 is user-programmable, it is ideal for evaluation of programs running in a m pd6124a or 6600a, and for small-scale production of such systems. the functions of the m pd61p24 are described in detail in the following users manual. be sure to read this manual before designing your system. m pd612x series users manual: iep-1083 features ? transmitter for programmable infrared remote control- ler ? 19 types of instructions ? instruction execution time: 17.6 m s (with 455-khz ce- ramic resonator) ? on-chip one-time prom: 1002 10 bits ? data memory (ram) capacity : 32 5 bits ? 9-bit programmable timer: 1 channel ? i/o pins (k i/o ): 8 pins ? input pins (k i ): 4 pins ? serial input pins (s-in): 1 pin ? transmission-in-progress indication pin (s-out): 1 pin ? transmit carrier frequency (rem) f osc /12, f osc /8 ? standby operation (halt/stop mode) ? low power consumption ? current consumption in stop mode (t a = 25 c) 1 m a max. ? low-voltage operation: v dd = 2.2 to 5.5 v 4-bit single-chip microcontroller for remote control transmission the information in this document is subject to change without notice. the mark shows major revised points. documen t no. u12629ej4v0ds00 (4th edition) previous no. ic-2876 date published july 1997 n printed in japan cautio n to use the nec transmission format, ask nec to supply the custom code. do no use r 0 when using a register as an operand of the branch instruction. 1997
m pd61p24 2 ordering information part number package m pd61p24cs 20-pin plastic shrink dip (300 mil) m pd61p24gs 20-pin plastic sop (300 mil) pin configuration (top view) (1) normal operating mode (2) prom programming mode k k s-in s-out rem v osc-out osc-in v ac 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 k k k k k k k k k k i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i0 i1 i2 i3 i/o1 i/o0 dd ss 1 2 3 4 5 6 7 8 d1 d0 v pp (open) (open) v dd (open) clk 20 19 18 17 16 15 14 13 d2 d3 d4 d5 d6 d7 md0 md1 9 v ss 12 md2 10 (l) 11 md3 caution round brackets ( ) indicate the pins not used in the prom programming mode. l : connect each of these pins to gnd via a resistor (470 w ). open: leave these pins open.
m pd61p24 3 block diagram i0 i3 k -k l h 32 5 bits ac k i/o0 -k i/o7 s-in rem s-out osc-in osc-out mod 10 bits osc rom d.p. rom d.p. pc(h) m p x add dec m p x ram ram cntl (h) cntl (l) sp timer (l) timer (h) acc key in key out(h) key out(l) alu watchdog timer function pc(l) one-time prom (l) one-time prom (h) 1002 10 bits
m pd61p24 4 1. program counter (pc) 10 bits the program counter (pc) is a binary counter, which holds the address information for the program memory. figure 1-1. program counter organization pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 pc 8 pc 9 pc normally, the program counter contents are automatically incremented each time an instruction is executed, according to the number of instruction bytes. when executing a jump instruction (jmp0, jc, jf), the program counter indicates the jump destination. immediate data or the data memory contents are loaded to all or some bits of the pc. when executing the call instruction (call0), the pc contents are incremented (+1) and saved into the stack memory. then, a value needed for each jump instruction will be loaded. when executing the return instruction (ret), the stack memory contents are double incremented (+2) and loaded into the pc. when all clear is input or on reset, the pc contents are cleared to 000h. 2. stack pointer (sp) 2 bits this 2-bit register holds the start address information for the stack area. the stack area is shared with the data memory. the sp contents are incremented, when the call instruction (call0) is executed. they are decremented, when the return instruction (ret) is executed. the stack pointer is cleared to 00b after reset or all clear is input, and indicates the highest address fh for the data memory as the stack area. the figure below shows the relationship for the stack pointer and the data memory area. r c data memory r d r e r f (sp) 11b 10b 01b 00b if the stack pointer overflows or underflows, it is determined that the cpu overflows, and the pc internal reset signal will be generated.
m pd61p24 5 3. program memory (rom) 1002 steps 10 bits the program memory (rom) is configured in 10 bits steps. it is addressed by the program counter. program and table data are stored in the program memory. figure 3-1. program memory map test program area 000h 0ffh 100h 1ffh 200h 2ffh 300h 3e9h 3eah 3ffh 4. data memory (ram) 32 words 5 bits the data memory is a ram of 32 words 5 bits. the data memory stores processing data. in some cases, the data memory is processed in 8-bit units. r 0 may be used as the data pointer for the rom. after power application, the ram will be undefined. the ram retains the previous data on reset. figure 4-1. data memory organization 1 r 0 0 r f r b r c sp? sp? sp? sp? . . . . . . caution avoid using the ram areas r d , r e , and r f in a call routine as much as possible because these areas are also used as stack memory areas (to prevent program hang-up in case the value of the sp is destroyed due to some reason such as noise). when using these ram areas as general-purpose ram areas, be sure to include stack pointer checking in the main routine.
m pd61p24 6 5. data pointer (r 0 ) r 0 (r 10 , r 00 ) for the data memory can serve as the data pointer for the rom. r 0 specifies the low-order 8 bits in the rom address. the high-order 2 bits in the rom address are specified by the control register. table referencing for rom data can be easily executed by calling the rom contents by setting the rom address to the data pointer. on reset or all clear is input, it becomes undefined. figure 5-1. data pointer organization ad 0 ad 1 ad 2 ad 3 ad 4 ad 5 ad 6 ad 7 ad 8 ad 9 control registers (p ) 1 r 0 r 10 r 00 6. accumulator (a) 4 bits the accumulator (a) is a 4-bit register. the accumulator plays a major role in each operation. on reset or all clear is input, it becomes undefined. figure 6-1. accumulator organization a 0 a 1 a 2 a 3 a 7. arithmetic logic unit (alu) 4 bits the arithmetic logic unit (alu) is a 4-bit operation circuit, and executes simple operations, such as arithmetic operations. 8. flags (1) status flag when the status for each pin is checked by the stts instruction, if the condition coincides with the condition specified by the stts instruction, the status flag (f) is set (to 1). on reset or all clear is input, it becomes undefined. (2) carry flag when the inc (increment) instruction or the rl (rotate left) instruction is executed, if a carry is generated from the msb for the accumulator, the carry flag (c) is set (to 1). the carry flag (c) is also set (to 1), if the contents for the accumulator are fh, when the scaf instruction is executed. on reset or all clear is input, it becomes undefined.
m pd61p24 7 9. system clock generator the system clock generator consists of a resonator, which uses a ceramic resonator (400khz to 500khz). figure 9-1. system clock generator stop mode system clock osc-out osc-in in the stop mode (oscillation stop halt instruction), the oscillator in the system clock generator stops its operation, and the system clock ? is stopped.
m pd61p24 8 10. timer the timer block determines the transmission output pattern. the timer consists of 10 bits, of which 9 bits serve as the 9-bit down counter and the remaining 1 bit serves as the 1-bit latch, which determines the carrier output validity. the 9-bit down counter is decremented (C1) every 8/f osc (s) in synchronization with the machine cycle, after starting down count operation. down counting stops after all of the 9 bits become 0. when down counting is stopped, the signal indicating that the timer operation has stopped, is output. if the cpu is at standby (halt timer) for the timer operation completion, the standby (halt) condition is released and the next instruction will be executed. if the next instruction again sets the value of the down counter, down counting continues without any error (the carrier output of the rem pin is not affected). set the down count time according to the following calculation; (set value (hex) + 1) 8/f osc . setting the value to the timer is done by the timer manipulation instruction. when the down counter is operating, the remote control transmission carrier can be output to the rem pin. whether or not to output the carrier can be selected by the msb for the timer register block. set 1, when outputting the carrier, or 0, when not outputting the carrier. if all the down counter bits become 0, when outputting the carrier, the carrier output will be stopped. when not outputting the carrier, the rem pin output will become low level. a signal in synchronization with the rem output is output to the s-out pin. however, the waveform for the s- out pin is low, when the carrier is being output to the rem pin, or it is high, when the carrier is not being output to the rem pin. if the halt instruction, which initiates the oscillation stop mode, is executed when the down counter is operating, the oscillation stop mode is initiated after down counting is stopped (after 0). timer operation stop/run is controlled by the control register (p 1 ). (refer to 13. control register (p 1 ) .) at reset (all clear) time, the rem pin goes low and s-out pin goes high. all 10 bits of the timer are cleared to 000h. caution because the timer clock is not synchronized with the carrier output, the pulse width may be shortened at the beginning and end of the carrier output. figure 10-1. timer block organization s-out rem carrier (fosc/12, fosc/8) selected by control register clear set by timer mainpulation instruction 9-bit down counter zero detection circuit d of control register p (timer run/stop) 21 1/0 msb fosc/8
m pd61p24 9 11. pin functions 11.1 k i/o pin (p 0 ) this is the 8-bit i/o pin for key-scan output. when the control register (p 1 ) is set for the input port, the port can be used as an 8-bit input pin. when the port is set for the input mode, all of these pins are pulled down to the v ss level inside the lsi. at reset (all cleared), the value of i/o mode and output latch becomes undefined. figure 11-1. k i/o pin organization k i/o7 k i/o6 k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 p 0 p 10 p 00 (p ) control register 1 11.2 k i/o pull-down resistor configuration v dd v ss cmos n-ch pin pull-down resistor input signal output signal input/output selection n-ch p-ch r when k i/o is set to the input mode, pull-down resistor r is turned on.
m pd61p24 10 11.3 k i pin (p 12 ) this is the 4-bit pin for key input. all of these pins are pulled down to the v ss level by pla data. figure 11-2. k i pin organization k i3 k i2 k i1 k i0 p 2 11.4 k i pull-down resistor configuration v dd v ss n-ch v ss pin input signal pla k i pull-down resistor switch pull-down resistor p-ch when the pull-down resistor switch is turned on (set 1) by pla data, pull-down resistor r is turned on.
m pd61p24 11 11.5 s-out pin by going low whenever the carrier frequency is output from the rem pin, the s-out pin indicates that communication is in progress. the s-out pin is cmos output. the s-out pin goes high on reset. 11.6 s-in pin (d 0 bit of p 1 ) to input serial data, use the s-in pin. when control register (p 1 ) is set to serial input mode, the s-in pin is connected as an input to the lsb of the accumulator; the s-in pin is pulled down to the v ss level within the lsi. in this state, if the rotate-left accumulator instruction (rl a) is executed, the data on the s-in pin is copied to the lsb of the accumulator. if the control register is released from serial input mode, the s-in pin goes into a high-impedance state, but no through current flows internally. when the rl a instruction is executed, the msb is copied to the lsb. at reset (all cleared), the s-in pin goes into a high-impedance state. figure 11-3. configuration of the s-in pin a 3 a 2 a 1 a 0 cy control register s-in
m pd61p24 12 12. port register (p ) k i/o , k i , and the control register are handled as port registers. the table below shows the relations between the port registers and pins. table 12-1. relations between port registers and pins pin input mode output mode name read write read write on reset k i/o pin status output latch pin status output latch undefined [input mode, output latch] k i pin status C C C input mode s-in pin status is read by rl a instruction when d 0 of p 1 register = 1. high impedance (d 0 of p 1 register = 0) p 10 p 11 p 12 p 00 p 01 p 02 k i/o7-4 k i/o3-0 p 0 p 1 p 2 control register (h) control register (l) k i3-0 p 1 (h) p 0 (l)
m pd61p24 13 13. control register (p 1 ) the control register contains of 10 bits. the controllable items are shown in table 13-1. table 13-1. control register (p 1 ) bit d 9 name test mode be sure to set 0. 0 1 set value timer d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 halt d.p. ad mod k i/o 9 d.p. ad 8 rl a a cc 0 ? stop nop f /8 ad =0 9 ad =0 8 osc in run osc stop f /12 ad =1 9 ad =1 8 osc out a 3 s-in d 0 .......................... specifies data to be input to a 0 when the accumulator is shifted to the left. 0: a 3 , 1:s-in d 1 .......................... specifies the status of k i/o , as follows: 0: input mode, 1: output mode d 2 .......................... specifies the status of the timer, as follows: 0: count stop, 1: count execution d 3 .......................... specifies the carrier frequency output from the rem pin. 0: f osc /8, 1: f osc /12 d 4 , d 5 ................. specify the high-order 2 bits of the rom data pointer. d 6 .......................... determines what happen to the oscillation circuit when the halt instruction is executed. 0: oscillation does not stop 1: oscillation stops (stop mode) d 7 .......................... be sure to set this bit to 0. d 8 , d 9 ................. these bits specify test modes. be sure to set them to 0. remark d 0 = d 8 = d 9 = 0 on reset, and the other bits are undefined.
m pd61p24 14 14. standby function (halt instruction) the m pd6600a is provided with the standby mode (halt instruction), in order to reduce the power consumption, when not executing the program. clock oscillation can be stopped in the standby mode (stop mode). in the standby mode, the program execution stops. however, the contents of the internal registers and the data memory are all retained. 14.1 stop mode (oscillation stop halt instruction) in the stop mode, the operation of the system clock generator (ceramic resonator oscillation circuit) stops. therefore, operations requiring the system clock will stop. if the halt instruction is executed during timer operation, the program counter stops. the oscillation stop mode will be initiated, after the timer count down operation is completed. 14.2 halt mode (oscillation continue halt instruction) the cpu stops its operation, until the halt release condition is satisfied. the system clock operation continues in this mode. 14.3 standby release conditions (1) s-in input (2) k i/o input (3) k i input (4) timer count down operation completion remark either high level or low level can be specified for setting a release condition by input. table 14-1. standby mode releasing condition d 3 0/1 0 releasing condition: 0 1 timer 01 00 k 0 0 s-in d 2 d 1 d 0 releasing condition 1 0 1 0 i/o k i remarks released when 0. valid only in the in mode. when rl a is selected, the standby mode is always released. 3 ? ?low level detection ?high level detection
m pd61p24 15 15. ac pin (all clear pin) internal part of the cpu including the program counter can be reset by setting the ac pin to the low level. watchdog timer function a power-on reset function and a cr watchdog timer function, that can be controlled by program, can be realized by connecting a 0.1 m f capacitor across the ac pin and the v ss . v dd 0.1 f m 0.1 f m v v dd v thl t charge mode charge start instruction execute halt instruction immediately before nop. (charge for 0.4 ms or more) discharge mode charge-discharge pattern discharge start instruction discharge starts after the nop instruction execution. (discharge time is about 5 ms from v dd to v thl ) the pattern must be controlled by the program, in such a manner that the c charge level will not go below v thl . caution when the watchdog timer function is not used, switch to charging mode by executing a nop instruction immediately before a halt instruction at the beginning of the program. (be sure to connect the capacitor.)
m pd61p24 16 16. mask options (pla data) the following items are fixed by mask option: ?k i , s-in pin pull-down resistor provided ? carrier duty selection (1/3) at f osc /12 ? hang-up detection provided <1> k i/o all the system is reset when the hang-up detection k i/o all switch is set to on (1) by pla data and if the k i/o pins are in the input mode in the oscillation stop halt mode or if even one of the k i/o pins is low. to use a pin as a key source of the switch, turn on the switch with pla data. figure 16-1. hang-up detection k i/o all configuration diagram v dd to reset circuit pla hang-up detection k i/o all switch k output signal i/o0 k output signal i/o1 k output signal i/o2 k output signal i/o3 k output signal i/o4 k output signal i/o5 k input/output selection i/o k output signal i/o6 k output signal i/o7 <2> halt release condition specification (s-in, k i/o , k i ) the system is reset if s-in and k i/o are used in the halt mode when s-in and k i/o are specified by pla data not to be used (1). k i is used (0).
m pd61p24 17 bit assignment by switch selection 0 1 2 7654 address note k i3 k i2 k i1 k i0 321 0 msb lsb ki pull-down resistor corresponding portion hang-up detection duty s-in 0 1 (provided) 1 (provided) 1 (provided) 1 (provided) 0 0 0 0 0 0 duty 1 (1/3 duty) s-in pull-down resistor 1 (provided) 1 (detection provided) 1 (unused) 1 (unused) 0 (used) k i/o all halt s-in halt k i/o halt k i 0
m pd61p24 18 17. writing, reading, and verifying one-time prom (program memory) to write, read, or verify the prom, set the prom mode and use the pins shown in table 17-1. no address input pin is used. to update the address, the clock signal input from the clk pin is used. table 17-1. pins used to write, read, and verify program memory symbol function v pp applies program voltage (12.5 v) clk inputs clock to update address md0-md3 selects operation mode d0-d7 inputs/outputs 8-bit data v dd applies supply voltage (6 v) 17.1 operation mode when writing, reading, and verifying program memory the m pd61p24 enters the program memory write, read, or verify mode if +6 v is applied to the v dd pin and +12.5 v is applied to the v pp pin after the reset status has been held a certain time (v dd = 5 v, ac = low level). in this mode, the operation modes listed in table 17-2 can be selected by using the md0 through md3 pins. any input pins not used for writing, reading, or verifying the program memory must be open or connected to gnd via a pull-down resistor (470 w ). table 17-2. operating mode when writing, reading, and verifying program memory specifies operation mode operation mode v pp v dd md0 md1 md2 md3 +12.5 v +6 v h l h l clears program memory address to 0 l h h h write mode l l h h read and verify modes h h h program inhibit mode : dont care (l or h)
m pd61p24 19 17.2 program memory writing procedure the program memory is written at high speed in the following procedure. (1) pull down the pins not used to gnd via resistor. keep the clk pin low. (2) supply 5 v to the v dd pin. keep the v pp pin low. (3) wait for 10 m s, and supply 5 v to the v pp pin. (4) set the mode in which the program memory address is cleared to 0, by using the mode setting pins. (5) supply 6 v to v dd and 12.5 v to v pp . (6) set the program inhibit mode. (7) write data in the 1-ms write mode. (8) set the program inhibit mode. (9) set the verify mode. if the data has been correctly written, proceed to (10). if not, repeat (7) through (9). (10) additional writing of (number of times data has been written in (7) through (9): x) 1 ms (11) set the program inhibit mode. (12) input a pulse four times to the clk pin to update the program memory address (+1). (13) repeat (7) through (12) until the data is written to the last address. (14) set the mode in which the program memory address is cleared to 0. (15) change the voltage on the v dd and v pp pins to 5 v. (16) turn off power supply. program memory writing steps (2) through (12) are illustrated below. write verify additional write address increment repeat x times md3 md2 md1 md0 d0-d7 clk gnd v dd v dd v dd +1 gnd v dd v pp v pp data input data output data input hi-z hi-z hi-z hi-z ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? reset
m pd61p24 20 17.3 program memory reading procedure (1) pull down the pins not used to gnd via resistor. keep the clk pin low. (2) supply 5 v to the v dd pin. keep the v pp pin low. (3) wait for 10 m s, and supply 5 v to the v pp pin. (4) set the mode in which the program memory address is cleared to 0, by using the mode setting pins. (5) supply 6 v to v dd and 12.5 v to v pp . (6) set the program inhibit mode. (7) set the verify mode. if a clock pulse is input to the clk pin, the data of one address is output each time the pulse has been input to the clk pin four times. (8) set the program inhibit mode. (9) set the mode in which the program memory address is cleared to 0. (10) change the voltage on the v dd and v pp pins to 5 v. (11) turn off power supply. program memory reading steps (2) through (9) are illustrated below. hi-z hi-z ?l md3 md2 md1 md0 d0-d7 clk gnd v dd v dd v pp v pp v dd gnd v dd +1 reset data output data output
m pd61p24 21 18. instruction set accumulator manipulation instructions anl anl anl anl orl orl orl orl xrl xrl xrl xrl inc rl d00 e00 a00 d10 d30 d31 e10 e30 e31 a10 a30 a31 a13 f13 r 10 r 11 r 12 r 1f r 00 r 01 r 0f r r a, r r a, @r 0 h a, @r 0 l a, #data a, r r a, @r 0 h a, @r 0 l a, #data a, r r a, @r 0 h a, @r 0 l a, #data a a d01 e01 a01 d02 e02 a02 d0f e0f a0f d20 e20 a20 d21 e21 a21 d2f e2f a2f input/output instructions p a, p , a, a, a, in out anl orl xrl f19 219 d19 e19 a19 p p 11 p p p a p p p p p p p f18 218 d18 e18 a18 p 10 f1a 21a d1a e1a a1z p 12 f39 239 d39 e39 a39 p 01 f38 238 d38 e38 a38 p 00 f3a 23a d3a e3a a3a 02 p out 319 p p 1 p p #data 318 p 0 31a p 2 p 1p and p 0p operate in pair format data transfer instructions mov mov f00 f10 f01 f02 f0f f20 f21 f2f a, r a, @r h r 0 r 10 r 11 r 12 r 1f r 00 r 01 r 0f r r mov f30 a, @r h 0 mov f31 a, #data mov mov 300 301 302 30f r , #data r , @r r r r 0 r 1 r 2 r f r r 320 321 322 32f mov r , a r 200 201 202 20f 220 221 22f 0 r 1r and r 0r operate in pair format
m pd61p24 22 branch instructions r r r 0 r 1 r 2 r f jmp0 jc jc jnc jnc jf jf jnf jnf addr addr rr note addr addr addr 411 611 631 711 731 rr note rr note rr note 601 621 701 721 602 622 702 722 60f 62f 70f 72f ? pair register jmp0 rr note 401 402 40f note r = 1 through f r = 0 canot be used. subroutine instructions addr call0 ret 411 p 1 p p 312 412 p 0 timer/counter manipulation instructions a, t , t, t, mov mov mov mov f1f 21f t 1 t t t a #data @r t 0 31f 33f t 0-1 t 0 t f3f 23f other instructions halt #data stts r stts #data scaf nop 00 r 111 131 d13 000 01 r 02 r 0f r 120 121 122 12f 0r
m pd61p24 23 19. application circuit example v dd v dd key matrix mode select switch infrared led se303 series se313 se307-c se1003-c transmission indication 2sc3616, 3618 2sd1615, 1616 2sc2001 3.0 v 47 f m + 100 pf 100 pf 0.1 f m k i/o1 k i/o0 s-in 1 2 3 4 5 6 7 8 9 10 k i/o2 k i/o3 s-out rem v dd osc-out osc-in v ss ac k i/o4 k i/o5 k i/o6 k i/o7 k i0 k i1 k i2 k i3 pd61p24 m 20 19 18 17 16 15 14 13 12 11 caution the ceramic resonator start up capacitor value must be determined, by taking the voltage level and the oscillation start up characteristics for the ceramic resonator into consideration.
m pd61p24 24 20. electrical specifications absolute maximum ratings (t a =25 c) parameter symbol ratings unit supply voltage v dd 7.0 v input voltage v in C0.3 to v dd + 0.3 v operating ambient temperature t a C20 to +75 c storage temperature t stg C40 to +125 c caution even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. the absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. be sure to use the product(s) within the ratings. recommended operating range (t a =25 c) parameter symbol min. typ. max. unit supply voltage v dd 2.2 5.5 v oscillation frequency f osc 400 500 khz
m pd61p24 25 dc characteristics (v dd = 3.0 v, f osc = 455 khz, t a =25 c) parameter symbol conditions min. typ. max. unit supply voltage v dd 2.2 5.5 v current consumption 1 i dd1 f osc = 455 khz 0.3 1.5 ma current consumption 2 i dd2 f osc = stop 1.0 m a rem high level output current i oh1 v o = 1.0 v C5 C8 C15 ma rem low level output current i ol1 v o = 0.3 v 0.5 1.5 2.5 ma s-out high level output current i oh2 v o = 2.7 v C0.3 C1.0 C2.0 ma s-out low level output current i ol2 v o = 0.3 v 1 1.5 2.5 ma ki high level input current i ih1 v i = 3.0 v 10 30 m a ki high level input current i ih1' v i = 3.0 v, without pull-down resistor 0.2 m a ki low level input current i il1 v i = 0 v C0.2 m a ki/o high level input current i ih2 v i = 3.0 v 10 30 m a ki/o high level input current i ih2' v i = 3.0 v, without pull-down resistor 0.2 m a ki/o low level input current i il2 v i = 0 v C0.2 m a ki/o high level output current i oh3 v 0 = 2.5 v C1.5 C2.0 C4.0 ma ki/o low level output current i ol3 v 0 = 2.1 v 25 50 100 m a s-in high level input current i ih3 v i = 3.0 v 6 15 m a s-in high level input current i ih3' v i = 3.0 v, without pull-down resistor 0.2 m a s-in low level input current i il3 v i = 0 v C0.2 m a ki high level input voltage v ih1 2.1 3.0 v ki low level input voltage v il1 v i = 3.0 v 0 0.9 v ki/o high level input voltage v ih2 1.3 3.0 v ki/o low level input voltage v il2 0 0.4 v s-in high level input voltage i ih3 1.1 3.0 v s-in low level input voltage i il3 0 0.4 v ac pull-up resistor r 1 v i = 0 v 0.3 3.0 k w ac pull-down resistor r 2 v i = 2.7 v 150 400 1500 k w ac high level input voltage v ih4 1.8 3.0 v ac low level input voltage v il4 0 1.2 v
m pd61p24 26 dc programming characteristics (t a = 25 5 c, v dd = 6.0 0.25 v, v pp = 12.5 0.5 v) parameter symbol conditions min. typ. max. unit high-level input voltage v ih1 other than clk 0.7 v dd v dd v v ih2 clk v dd C0.5 v dd v low-level input voltage v il1 other than clk 0 0.3 v dd v v il2 clk 0 0.4 v input leakage current i li v in = v il or v ih 10 m a high-level output voltage v oh i oh = C1 ma v dd C1.0 v low-level output voltage v ol i ol = 1.6 ma 0.4 v v dd supply current i dd 30 ma v pp supply current i pp md0 = v il , md1 = v ih 30 ma cautions 1. keep v pp to within +13.5 v including the overshoot. 2. apply v dd before v pp , and turn it off after v pp . ac programming characteristics (t a = 25 5 c, v dd = 6.0 0.25 v, v pp = 12.5 0.5 v) parameter symbol note 1 conditions min. typ. max. unit address setup time note 2 (vs. md0 )t as t as 2 m s md1 setup time (vs. md0 )t m1s t oes 2 m s data setup time (vs. md0 )t ds t ds 2 m s address hold time note 2 (vs. md0 - )t ah t ah 2 m s data hold time (vs. md0 - )t dh t dh 2 m s md0 -? data output float delay time t df t df 0 130 ns v pp setup time (vs. md3 - )t vps t vps 2 m s v dd setup time (vs. md3 - )t vds t vcs 2 m s initial program pulse width t pw t pw 0.95 1.0 1.05 ms additional program pulse width t opw t opw 0.95 21.0 ms md0 setup time (vs. md1 - )t m0s t ces 2 m s md0 ? data output delay time t dv t dv md0 = md1 = v il 1 m s md1 hold time (vs. md0 - )t m1h t oeh t m1h + t m1r 3 50 m s2 m s md1 recovery time (vs. md0 )t m1r t or 2 m s program counter reset time t pcr 10 m s clk input high-, low-level widths t xh , t xl 0.125 m s clk input frequency f x 4.19 mhz initial mode set time t i 2 m s md3 setup time (vs. md1 - )t m3s 2 m s md3 hold time (vs. md1 )t m3h 2 m s md3 setup time (vs. md0 )t m3sr on reading program memory 2 m s address note 2 ? data output delay time t dad t acc on reading program memory 2 m s address note 2 ? data output hold time t had t oh on reading program memory 0 130 ns md3 hold time (vs. md0 - )t m3hr on reading program memory 2 m s md3 ? data output float delay time t dfr on reading program memory 2 m s reset setup time t res 10 m s notes 1. corresponding symbols of m pd27c256a (the m pd27c256a is a maintenance product). 2. the internal address signal is incremented by one at the falling edge of clk input at the third clock.
m pd61p24 27 program memory write timing program memory read timing v pp v pp v dd gnd v dd +1 v dd v dd gnd clk d0-d7 md0 md1 md2 md3 t res t vps t vds t xh t xl t as t ah t dh t ds t opw t df t dv t m0s t m1r t oh t ds t pw t i t m3h t m1h t m1s t pcr t m3s data input data output data input data input hi-z hi-z hi-z hi-z hi-z data output data output t m3sr t pcr t dv t i t xl t dad t had t vds t vps t xh t m3hr t dfr ?l v pp v pp v dd gnd v dd +1 v dd v dd gnd clk d0-d7 md0 md1 md2 md3 t res hi-z hi-z
m pd61p24 28 21. package drawings 20 pin plastic sop (300 mil) item millimeters inches a b c e f g h i j 13.00 max. 1.27 (t.p.) 1.8 max. 1.55 7.7?.3 0.78 max. 0.12 1.1 5.6 m 0.1?.1 n 0.512 max. 0.031 max. 0.004?.004 0.071 max. 0.061 0.303?.012 0.220 0.043 0.005 0.050 (t.p.) p20gm-50-300b, c-4 p 3 3 +7 note each lead centerline is located within 0.12 mm (0.005 inch) of its true position (t.p.) at maximum material condition. d 0.40 0.016 +0.10 ?.05 k 0.20 0.008 +0.10 ?.05 l 0.6?.2 0.024 0.10 ? +7 ? 0.004 +0.008 ?.009 +0.004 ?.002 +0.004 ?.003 a c d g p detail of lead end f e b h i l k m j n m 1 1 0 1 1 20
m pd61p24 29 20pin plastic shrink dip (300 mil) item millimeters inches notes 1) each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. p20c-70-300b-1 n 0.17 0.007 r 0~15 0~15 a 19.57 max. 0.771 max. b 1.78 max. 0.070 max. f 0.85 min. 0.033 min. g 3.2?.3 0.126?.012 j 5.08 max. 0.200 max. k 7.62 (t.p.) 0.300 (t.p.) c 1.778 (t.p.) 0.070 (t.p.) d 0.50?.10 0.020 +0.004 ?.005 h 0.51 min. 0.020 min. i 4.31 max. 0.170 max. l 6.5 0.256 m 0.25 0.010 +0.004 ?.003 +0.10 ?.05 2) ltem "k" to center of leads when formed parallel. m r m i h g f dn c b k 110 20 11 a l j
m pd61p24 30 22. recommended soldering conditions it is recommended that m pd6124a and 6600a be soldered under the following conditions. for details on the recommended soldering conditions, refer to information document, semiconductor device mounting technology manual (c10535e) . for other soldering methods and conditions, consult nec. table 22-1. soldering conditions of surface-mount type m pd61p24gs: 20-pin plastic sop (300 mil) soldering method soldering conditions partial heating pin temperature: 300 c max., time: 3 seconds max. (per device side) table 22-2. soldering conditions of through-hole type m pd61p24cs: 20-pin plastic shrink dip (300 mil) soldering method soldering conditions wave soldering (only for pin part) solder bath temperature: 260 c max., time: 10 seconds max. partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin) caution when soldering this product using of wave soldering, exercise care that the solder does not come in direct contact with the package.
m pd61p24 31 appendix a. m pd612 series product list part number m pd6124a m pd6600a m pd61p24 m pd6125a m pd6126a item rom capacity 1002 10 bits 512 10 bits 1002 10 bits 1002 10 bits (mask rom) (mask rom) (one-time prom) (mask rom) ram capacity 32 5 bits i/o pin 8 pins (k i/o0-7 ) 12 pins 16 pins (k i/o0-7 , (k i/o0-7 , i/o 00-03 ) i/o 00-03 , i/o 10-13 ) s-in pin provided current consumption 2 m a1 m a (f osc = stop) (max.) s-in high-level input 30 m a 15 m a current (max.) transmission carrier frequency f osc /12, f osc /8 low-voltage detection provided none (reset) function mask option provided none (fixed) provided supply voltage v dd = 2.2 to 5.5 v v dd = 2.2 to 3.6 v v dd = 2.2 to 5.5 v v dd = 2.0 to 6.0 v package ? 20-pin plastic sop (300 mil) ? 24-pin plastic ? 28-pin plastic ? 20-pin plastic shrink dip (300 mil) sop (300 mil) sop (375 mil) ? 24-pin plastic shrink dip (300 mil)
m pd61p24 32 appendix b. development tools the following tools are available for program development using the m pd61p24. document document no. m ps612x series emulator note 1 m ps61p24 assembler note 1 prom programmer af-9703 note 2, 3 af-9704 note 2, 3 af-9705 note 3 af-9706 note 3 m pd61p24 program adapter af9807b note 3 notes 1. these are products from i.c corp. for details, consult i.c corp. i.c corp. 6th barnet gotanda bldg. 1-9-5 higashi-gotanda, shinagawa-ku, tokyo 141 tel. 03-3447-3793 fax. 03-3440-5606 2. not available. 3. these are products from ando electric co., ltd. for details, consult ando electric co., ltd. ando electric co., ltd. 4-19-7 kamata, ota-ku, tokyo 144 tel. 0120-40-0211(toll-free) caution use a writing program after assembling the program, convert the hex file to a rom file by using the prom utility program updprom (refer to as612x assembler users manual(iem-1016)).
m pd61p24 33 [memo]
m pd61p24 34 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
m pd61p24 35 nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8
m pd61p24 36 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. the application circuits and their parameters are for reference only and are not intended for use in actual design-ins. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 [memo]

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